library verilog;
use verilog.vl_types.all;
entity TLC_DA is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        data_in         : in     vl_logic_vector(10 downto 0);
        da_data         : out    vl_logic;
        da_clk          : out    vl_logic;
        da_ldac         : out    vl_logic;
        da_load         : out    vl_logic
    );
end TLC_DA;
